/home/hillier_g/checkout/most4linux/libnetservices/include/smsc/mostdef1.h

00001 /*
00002 ==============================================================================
00003 
00004 Project:        MOST NetServices 
00005 Module:         Definition File for MOST NetServices Basic Layer
00006 File:           MostDef1.h
00007 Version:        1.10.03 
00008 Language:       C
00009 Author(s):      S.Kerber
00010 Date:           25.Feb.2005
00011 
00012 FileGroup:      Layer I
00013 Customer ID:    20D0FF0B011003.N.SIERE
00014 FeatureCode:    FCR1
00015 ------------------------------------------------------------------------------
00016 
00017                 (c) Copyright 1998-2005
00018                 Oasis SiliconSystems AG
00019                 All Rights Reserved
00020 
00021 ------------------------------------------------------------------------------
00022 
00023 
00024 
00025 Modifications
00026 ~~~~~~~~~~~~~
00027 Date    By      Description
00028 
00029 ==============================================================================
00030 */
00031 
00032 
00033 #ifndef _MOSTDEF1_H
00034 #define _MOSTDEF1_H
00035 
00036 
00037 
00038 
00039 
00040 //-------------------------------------------------------------------
00041 //  Data Type Definitions
00042 //-------------------------------------------------------------------
00043 #ifndef USE_OWN_TYPE_DEFINITION // Using basic type definition of NetServices ?
00044 #ifndef __cplusplus
00045 typedef unsigned char bool;
00046 #endif
00047 typedef unsigned char byte;
00048 typedef unsigned short int word;
00049 typedef unsigned long int dword;
00050 #endif
00051 
00052 
00053 
00054 //-------------------------------------------------------------------
00055 //  General Definitions
00056 //-------------------------------------------------------------------
00057 
00058 #ifndef _CONST                  // not defined in adjust.h ?
00059  #ifdef _WIN32
00060     #define _CONST              // define dummy
00061  #else
00062     #define _CONST const
00063  #endif
00064 #endif
00065 
00066 #ifndef TRUE
00067     #define TRUE        0x01
00068 #endif
00069 #ifndef FALSE
00070     #define FALSE       0x00
00071 #endif
00072 #ifndef ON
00073     #define ON          0x01
00074 #endif
00075 #ifndef OFF
00076     #define OFF         0x00
00077 #endif
00078 #ifndef HIGH
00079     #define HIGH        0x01
00080 #endif
00081 #ifndef LOW
00082     #define LOW         0x00
00083 #endif
00084 #ifndef NIL
00085     #define NIL         0x0000
00086 #endif
00087 #ifndef NULL
00088    #define NULL         ((void *)0)
00089 #endif
00090 #ifndef ENABLE
00091     #define ENABLE      0x01
00092 #endif
00093 #ifndef DISABLE
00094     #define DISABLE     0x00
00095 #endif
00096 
00097 
00098 #ifdef TIMER_INT_OPT            // MostTimerIntDiff() is used instead of MostTimerInt()
00099     #ifdef TIMER_INT_DIV
00100     #undef TIMER_INT_DIV
00101     #define TIMER_INT_DIV   1   // Timer values are divided by 1ms, but there is no need to call
00102     #endif                      // MostTimerIntDiff() in a strict 1ms interval
00103 #endif
00104 
00105 #if (TIMER_INT_DIV != 1) && (TIMER_INT_DIV != 10) && (TIMER_INT_DIV != 25)
00106     #error Please select TIMER_INT_DIV as 1, 10, or 25
00107 #endif                                        
00108 
00109 
00110 
00111 #define MOST_BROADCAST_ADDRESS  0x03C8      // Broadcast Address on MOST control channel
00112 
00113 
00114 //-----------------------------------------------------------------//
00115 //  Debug Interface                                                //
00116 //-----------------------------------------------------------------//
00117 
00118 // General:
00119 //-----------------
00120 #ifndef MNS_DBG_LEVEL
00121     #define MNS_DBG_LEVEL   0   // no debug messages
00122 #endif
00123 
00124 
00125 //-------------------------------------------------------------------
00126 //  Macros for getting Highbyte and Lowbyte of a 16 bit value
00127 //-------------------------------------------------------------------
00128 #ifndef HB
00129     #define HB(value)   (byte)((value)>>8)
00130 #endif
00131 
00132 #ifndef LB
00133     #define LB(value)   (byte)((value)&0xFF)
00134 #endif
00135 
00136 
00137 //-------------------------------------------------------------------
00138 //  Macros for differentiate NIC revisions
00139 //-------------------------------------------------------------------
00140 
00141 #define NIC_REV_8104A (Most_Revision[0] >= 0x14)
00142 
00143 //-------------------------------------------------------------------
00144 //  Interface IDs
00145 //-------------------------------------------------------------------
00146 #define INTF_CTRL   0x01
00147 #define INTF_ASYNC  0x02
00148 
00149 //-------------------------------------------------------------------
00150 //  Filter IDs
00151 //-------------------------------------------------------------------
00152 #ifndef CTRL_FILTER_ID_DEFAULT
00153   #define CTRL_FILTER_ID_DEFAULT    0xFF
00154 #endif
00155 
00156 
00157 //-------------------------------------------------------------------
00158 //  Errors on function call (Return values)
00159 //-------------------------------------------------------------------
00160 #define ERR_NO          0x00                // no error occurred
00161 #define ERR_PARAM       0x01                // wrong parameter(s)
00162 #define ERR_NOMSG       0x02                // no rx message available
00163 #define ERR_BUFOV       0x04                // tx buffer overflow
00164 #define ERR_NOTAVAIL    0x08                // functionality not available
00165 
00166 
00167 //-------------------------------------------------------------------
00168 //  Buffer Status Flags
00169 //-------------------------------------------------------------------
00170 #define BUF_FREE            0x00
00171 #define BUF_F_LOCK          0x01
00172 #define BUF_F_READY         0x02
00173 #define BUF_F_ACTIVE        0x04
00174 #define BUF_F_RXTRIGGER     0x08    // RX section only
00175 #define BUF_F_TXRETRY       0x08    // TX section only
00176 
00177 #define BUF_F_GBGCOL        0x10    // RX section only
00178 #define BUF_F_TXINTTGT      0x20    // TX section only; transmitted only to internal target
00179 
00180 
00181 
00182 //-------------------------------------------------------------------
00183 //  Macros to set a request for MostService()
00184 //-------------------------------------------------------------------
00185 #ifdef MNS_OPT_1
00186 #define MNS_REQUEST_SET(flags)      MnsPendingSet(flags);
00187 #define MNS_REQUEST_CALL(flags)     MnsPendingSetAndCall(flags);
00188 #else
00189 #define MNS_REQUEST_SET(flags)
00190 #define MNS_REQUEST_CALL(flags)
00191 #endif
00192 
00193 
00194 //-------------------------------------------------------------------
00195 //  Macros to set a request for MostServiceAsync()
00196 //-------------------------------------------------------------------
00197 #if (defined ADS_TX_MIN) || (defined ADS_RX_MIN)
00198 #ifdef MNS_OPT_1
00199 #define MNS_REQUEST_ASYNC_SET(flags)        MnsPendingAsyncSet(flags);
00200 #define MNS_REQUEST_ASYNC_CALL(flags)       MnsPendingAsyncSetAndCall(flags);
00201 #else
00202 #define MNS_REQUEST_ASYNC_SET(flags)
00203 #define MNS_REQUEST_ASYNC_CALL(flags)
00204 #endif
00205 #endif
00206 
00207 
00208 
00209 //-------------------------------------------------------------------
00210 //  Interrupts, which are enabled after Reset
00211 //
00212 //-------------------------------------------------------------------
00213 #ifndef INT_ENABLE_AFTER_RESET
00214  #define INT_ENABLE_AFTER_RESET     0xF     // all events are enabled
00215 #endif
00216 
00217 
00218 //----------------------------------------------------------------------
00219 // MOST Supervisor
00220 //------------------------------------
00221 #if (defined MSV_MINIMUM) && (defined MSV_EXTENDED)
00222     #undef MSV_MINIMUM
00223 #endif
00224 
00225 #if (defined MSV_MINIMUM) && (defined SERVICE_LAYER_II)
00226     #error Minimum Supervisor does not support LayerII
00227 #endif 
00228 
00229 //----------------------------------------------------------------------
00230 //  Secondary Node Solution
00231 //----------------------------------------------------------------------
00232 #ifdef SECONDARY_NODE
00233 
00234     #ifndef SECONDARY_NODE_INT_ENABLE   // define default value of secondary node IE register:
00235       #ifdef SECONDARY_NODE_OPT_1       // if secondary node is in front of primary node
00236         #define SECONDARY_NODE_INT_ENABLE   0x05    // Enable Interrupts: IERR + IMRX
00237       #else
00238         #define SECONDARY_NODE_INT_ENABLE   0x01    // Enable Interrupt:  IMRX
00239       #endif
00240     #endif
00241 
00242     #undef  INTERFACE_CONFIG
00243     #define INTERFACE_CONFIG 0          // ignore definition of user, if secondary node scenario
00244 
00245     #ifdef MOST_TRANSCEIVER_ID
00246         #if (MOST_TRANSCEIVER_ID != 1) &&  (MOST_TRANSCEIVER_ID != 5) &&  (MOST_TRANSCEIVER_ID != 7)   // neither OS8104 nor OS8104A ?
00247             #undef MOST_TRANSCEIVER_ID
00248             #error Secondary Node Solution is only provided for OS8104 and OS8104A  --> Select correct MOST_TRANSCEIVER_ID
00249         #endif
00250     #endif
00251 
00252     #if (defined MSV_MINIMUM) || (defined MSV_VIRTUAL)
00253         #error Secondary Node Solution is only provided for Extended Supervisor
00254     #endif
00255 
00256 #else
00257     #undef SECONDRY_NODE_OPT_1
00258 #endif //SECONDARY_NODE
00259 
00260 
00261 
00262 //----------------------------------------------------------------------
00263 //  Prepare Switches for Control Port Communication
00264 //  and Source Port Configuration
00265 //----------------------------------------------------------------------
00266 #if     (INTERFACE_CONFIG == 1)
00267         #define CP_I2C
00268         #define SP_SER
00269 #endif
00270 #if     (INTERFACE_CONFIG == 2)
00271         #define CP_SPI
00272         #define SP_SER
00273 #endif
00274 #if     (INTERFACE_CONFIG == 3)
00275         #define CP_I2C
00276         #define SP_PAR
00277 #endif
00278 #if     (INTERFACE_CONFIG == 4)
00279         #define CP_SPI
00280         #define SP_PAR
00281 #endif
00282 #if     (INTERFACE_CONFIG == 5)
00283         #define CP_I2C
00284         #define SP_PAR
00285         #define PADT
00286 #endif
00287 #if     (INTERFACE_CONFIG == 6)
00288         #define CP_SPI
00289         #define SP_PAR
00290         #define PADT
00291 #endif
00292 #if     (INTERFACE_CONFIG == 7)
00293         #define CP_PAR
00294         #define SP_PAR
00295 #endif
00296 #if     (INTERFACE_CONFIG == 8)
00297         #define CP_PAR
00298         #define SP_PAR
00299         #define PADT
00300 #endif
00301 #if     (INTERFACE_CONFIG == 9)
00302         #define CP_COM
00303         #define SP_SER
00304 #endif
00305 
00306 #ifdef RE_MSG_INTF
00307         #undef  SCS_NO_ADDR_CALC
00308         #undef  SP_SER
00309         #undef  SP_PAR
00310         #define SP_SERPAR
00311 #endif
00312 
00313 
00314 //----------------------------------------------------------------------
00315 //  Prepare Switches to identify different types of MOST Transceiver
00316 //      - OS8104        (active on OS8104, OS8104A)
00317 //      - OS8104A       (active on OS8104A)
00318 //      - OS8401        (active on OS8401, OS8801, OS8804, OS8805)
00319 //      - OS8805        (active on OS8805)
00320 //----------------------------------------------------------------------
00321 
00322 #ifndef MOST_TRANSCEIVER_ID     // Prepare the default settings, if not specified by user:
00323 
00324     #if (INTERFACE_CONFIG == 0)                                 // Secondary Node Scenario
00325         #define OS8104
00326     #endif
00327 
00328     #if ((INTERFACE_CONFIG >= 1) && (INTERFACE_CONFIG <= 8))    // Single Chip Solution with OS8104
00329         #define OS8104
00330     #endif
00331 
00332     #if (INTERFACE_CONFIG == 9)
00333         #define OS8401                                          // OS8401, OS8801, OS8804, OS8805
00334     #endif
00335 
00336 #endif
00337 
00338 #ifdef MOST_TRANSCEIVER_ID
00339 
00340     #if (MOST_TRANSCEIVER_ID == 1)  // OS8104
00341         #define OS8104
00342     #endif
00343 
00344     #if (MOST_TRANSCEIVER_ID == 2)  // OS8401 or OS8801
00345         #define OS8401
00346     #endif
00347 
00348     #if (MOST_TRANSCEIVER_ID == 3)  // OS8804
00349         #define OS8401              //        inherit OS8401
00350     #endif
00351 
00352     #if (MOST_TRANSCEIVER_ID == 4)  // OS8805
00353         #define OS8401              //        inherit OS8401
00354 
00355 
00356         #ifndef OS8805        
00357           #define OS8805            //        plus new features of OS8805
00358         #endif
00359     #endif
00360 
00361     #if (MOST_TRANSCEIVER_ID == 5)  // OS8104A
00362         #define OS8104              //        inherit OS8104
00363         #define OS8104A             //        plus new features of OS8104A
00364     #endif
00365 
00366 
00367     #if (MOST_TRANSCEIVER_ID == 7)  // OS8104A_DYN
00368         #define OS8104              //        inherit OS8104
00369         #define OS8104A             //        plus new features of OS8104A
00370         #define OS8104A_DYN         //        plus dynamic distinction
00371     #endif
00372 
00373 
00374 #endif
00375 
00376 //----------------------------------------------------------------------
00377 // Plausibility check:  MOST_TRANSCEIVER_ID vs. INTERFACE_CONFIG
00378 //----------------------------------------------------------------------
00379 
00380 #ifdef OS8104   // 8104, 8104A:
00381         #if (INTERFACE_CONFIG == 9)
00382             #error OS8104 and OS8104A do not support INTERFACE_CONFIG 9
00383         #endif
00384 #endif
00385 
00386 #ifdef OS8401   // OS8401, OS8801, OS8804, OS8805:
00387         #if (INTERFACE_CONFIG != 9)
00388             #error OS8401, OS8801, OS8804, and OS8805 do only support INTERFACE_CONFIG 9
00389         #endif
00390 #endif
00391 
00392 
00393 
00394 
00395 
00396 
00397 
00398 
00399 //----------------------------------------------------------------------
00400 // RingBreakDiagnosis Timeout Values:
00401 //----------------------------------------------------------------------
00402 // The default diagnosis base timeout value (30sec.) can be modified by
00403 // an optional macro MSV_TIMEOUT_DIAGNOSIS that can be defined in
00404 // adjust.h if desired by the system integrator.
00405 // For the alternative diagnosis mode (MSV_DIAG_EXT) this value is just
00406 // fixed to 3900 ms currently.
00407 // ==> RBD base timeout values:   MSV_TIMEOUT_DIAGNOSIS and MSV_TIMEOUT_DIAGNOSIS_DELTA
00408 
00409 #ifndef MSV_DIAG_EXT    // Standard Ringbreak Diagnosis:
00410     #define MSV_TIMEOUT_DIAGNOSIS_DEF   30000   // Default value: 30 sec.  (=TIME_D_SLAVE)
00411     #define MSV_TIMEOUT_DIAGNOSIS_MIN   4000    // Min value: 4 sec.
00412     #define MSV_TIMEOUT_DIAGNOSIS_MAX   60000   // Max value: 60 sec.
00413     #define MSV_TIMEOUT_DIAGNOSIS_DELTA 2000    // Delta between TIME_D_SLAVE and
00414 #endif
00415 
00416 #ifdef MSV_DIAG_EXT     // Alternative Diagnosis Mode:
00417     #define MSV_TIMEOUT_DIAGNOSIS_DEF   3900    // Defaultvalue = 3900 ms  (=TIME_D_SLAVE
00418     #define MSV_TIMEOUT_DIAGNOSIS_MIN   3900    // Min value: 3.9 sec.
00419     #define MSV_TIMEOUT_DIAGNOSIS_MAX   3900    // Max value: 3.9 sec.
00420     #define MSV_TIMEOUT_DIAGNOSIS_DELTA 1900    // Delta between TIME_D_SLAVE and TIME_D_MASTER
00421 #endif
00422 
00423 // Check for correct value of MSV_TIMEOUT_DIAGNOSIS:
00424 #ifndef MSV_TIMEOUT_DIAGNOSIS
00425     #define MSV_TIMEOUT_DIAGNOSIS  MSV_TIMEOUT_DIAGNOSIS_DEF    // Default value: 30 sec.
00426 #else
00427   #if (MSV_TIMEOUT_DIAGNOSIS < MSV_TIMEOUT_DIAGNOSIS_MIN)       // Check valid range
00428     #undef MSV_TIMEOUT_DIAGNOSIS
00429     #define MSV_TIMEOUT_DIAGNOSIS  MSV_TIMEOUT_DIAGNOSIS_MIN
00430   #endif
00431   #if (MSV_TIMEOUT_DIAGNOSIS > MSV_TIMEOUT_DIAGNOSIS_MAX)
00432     #undef MSV_TIMEOUT_DIAGNOSIS
00433     #define MSV_TIMEOUT_DIAGNOSIS  MSV_TIMEOUT_DIAGNOSIS_MAX
00434   #endif
00435 #endif
00436 
00437 
00438 
00439 
00440 
00441 //----------------------------------------------------------------------
00442 // MOST Supervisor Timeout Values:
00443 //----------------------------------------------------------------------
00444 #define TIME_LOCK           (  100/TIMER_INT_DIV)           // timeout value in milliseconds
00445 #define TIME_D_LOCK         (  250/TIMER_INT_DIV)           //
00446 #define TIME_OFF            (  300/TIMER_INT_DIV)           //
00447 #define TIME_SLAVE          ( 2000/TIMER_INT_DIV)           //
00448 #define TIME_MASTER         ( 2000/TIMER_INT_DIV)           //
00449 #define TIME_NCE_DELAY      (  100/TIMER_INT_DIV)           //
00450 #define TIME_D_SLAVE        ( (MSV_TIMEOUT_DIAGNOSIS) / TIMER_INT_DIV)
00451 #define TIME_D_MASTER       ( ((MSV_TIMEOUT_DIAGNOSIS) - (MSV_TIMEOUT_DIAGNOSIS_DELTA)) / TIMER_INT_DIV)
00452 #define TIME_D_DELTA        ( (MSV_TIMEOUT_DIAGNOSIS_DELTA) / TIMER_INT_DIV)
00453 
00454 
00455 
00456 
00457 
00458 #ifdef MSV_RBD_OPT1  // switch just used for downward compatibility (no longer needed in adjust.h)
00459     #ifndef MSV_TIME_D_RESTART
00460         #define MSV_TIME_D_RESTART  5000    // Defaultvalue: 5 sec.
00461     #endif
00462 #else
00463     #ifndef MSV_TIME_D_RESTART
00464         #define MSV_TIME_D_RESTART  0       // Defaultvalue: 0 sec.
00465     #endif
00466 #endif  
00467 
00468 #define TIME_D_RESTART      (  (MSV_TIME_D_RESTART) /TIMER_INT_DIV)
00469 
00470 
00471 #define TIME_PASP_ACCESS ( 50/TIMER_INT_DIV)            //
00472 
00473 #if (TIMER_INT_DIV == 25)
00474     #define TIME_UNLOCK 3                               // 75 ms
00475 #else
00476  #if (TIMER_INT_DIV == 10)
00477     #define TIME_UNLOCK 7                               // 70 ms
00478  #else
00479     #define TIME_UNLOCK 70                              // 70 ms
00480  #endif
00481 #endif
00482 
00483 #if (TIMER_INT_DIV == 25)
00484     #define TIME_NPR_VALID 3                            // 75 ms
00485 #else
00486  #if (TIMER_INT_DIV == 10)
00487     #define TIME_NPR_VALID 7                            // 70 ms
00488  #else
00489     #define TIME_NPR_VALID 70                           // 70 ms
00490  #endif
00491 #endif
00492 
00493 
00494 //--------------------------------------------
00495 // Zero Power
00496 //--------------------------------------------
00497 #ifdef TIME_ZEROPOWER_DELAY         // Time in ms
00498     #define TIME_ZP_DEL (TIME_ZEROPOWER_DELAY /TIMER_INT_DIV)
00499 #else
00500     #define TIME_ZP_DEL  (150/TIMER_INT_DIV)
00501 #endif
00502 
00503 
00504 
00505 
00506 //-------------------------------------------------------------------
00507 //  Circumference of Net Services
00508 //  (will be prepared automatically after adjusting the NetServices)
00509 //-------------------------------------------------------------------
00510 
00511 
00512 // MOST Net Service Kernel
00513 //------------------------------------
00514 #ifdef MNS_MIN                                          // minimum requirement of MOST NetServices
00515         #define MNS_0
00516         #define MNS_1
00517         #define MNS_50
00518 
00519         #ifdef TIMER_INT_OPT
00520          #define MNS_4          // MnsTimerIntDiff()
00521         #else
00522          #define MNS_2          // MnsTimerInt()
00523         #endif
00524 
00525         #if (defined ADS_TX_MIN) || (defined ADS_RX_MIN)    // only needed if ADS is implemented
00526          #define MNS_3
00527         #endif
00528 
00529         #ifdef MSV_EXTENDED                                 // software timer of Extended Supervisor
00530          #define MNS_21
00531          #define MNS_22
00532          #define MNS_23
00533          #define MNS_27
00534          #define MNS_28
00535          #define MNS_30
00536 
00537         #ifdef MSV_ADD10
00538           #ifdef OS8805
00539             #define MNS_32                                  // Rx/Crystal/Rx switch Timer (PLL limiting)
00540           #endif
00541         #endif
00542 
00543         #endif
00544 
00545 
00546         #ifdef MSV_MINIMUM
00547          #define MNS_23
00548         #endif
00549 
00550         #ifdef AMS_RX_MIN                                   // software timer of AMS
00551         #ifndef AMS_RX_NOSEG
00552          #define MNS_24
00553         #endif
00554         #endif
00555 
00556 
00557         #ifdef AMS_TX_ADD9                                  // mid level retry timer
00558           #define MNS_29
00559 
00560           #if (TIME_MSG_TX_RETRY > TIMER_INT_DIV)
00561               #define TIME_MID_LEVEL_RETRY ((word)(TIME_MSG_TX_RETRY/TIMER_INT_DIV))
00562           #else
00563               #define TIME_MID_LEVEL_RETRY ((word)1)                        // avoid loading timer with value 0
00564           #endif
00565 
00566         #endif
00567 
00568         #ifdef CMS_TX_MIN
00569          #define MNS_25                                     // software timer of CMS Tx Section
00570         #endif
00571 
00572         #ifdef ADS_TX_MIN
00573          #define MNS_26                                     // software timer of ADS Tx Section
00574 
00575         #endif
00576 
00577 
00578 #ifdef MNS_OPT_1                                        // Option 1: Request Flags
00579         #define MNS_10
00580         #define MNS_11
00581         #define MNS_40
00582         #define MNS_CB1
00583         #define MNS_CB3
00584 
00585      #if (defined ADS_TX_MIN) || (defined ADS_RX_MIN)   // only needed if ADS is implemented
00586          #define MNS_12
00587          #define MNS_13
00588          #define MNS_CB2
00589          #define MNS_CB4
00590      #endif
00591 #endif
00592 
00593 #ifdef MNS_OPT_3
00594     #ifdef TIMER_INT_OPT                                // Only available if using MostTimerIntDiff()
00595         #define MNS_41                                  // Function to get lowest timer value
00596     #endif
00597 #endif
00598 
00599 
00600 #ifdef MNS_MSG_INTF                                     // Message based interface to HW layer
00601     #define V_MNS_60
00602     #define V_MNS_61
00603 #endif
00604 
00605 #if (MNS_DBG_LEVEL > 0)
00606     #define MNS_CB10                                    // callback to present the debug messages
00607 #endif
00608 
00609 #endif  // MNS_MIN
00610 
00611 
00612 
00613 // Control Message Service Tx Section
00614 //------------------------------------
00615 #ifdef CMS_TX_MIN                                       // minimum requirement
00616         #define CMS_0
00617         #define CMS_T1
00618         #define CMS_T2
00619         #define CMS_T3
00620         #define CMS_T4
00621         #define CMS_T5
00622         #define CMS_T10
00623         #define CMS_T13
00624         #define CMS_T14
00625         #define CMS_CB1
00626 
00627 #ifdef CMS_MSG_INTF         // Message based interface
00628         #define V_CMS_T6
00629         #define V_CMS_T7
00630         #define V_CMS_T20
00631         #define V_CMS_T21
00632 #else                       // Register based interface
00633         #define CMS_T6
00634         #define CMS_T7
00635         #define CMS_T20
00636         #define CMS_T21
00637 #endif // CMS_MSG_INTF
00638 
00639 
00640 #ifdef CMS_TX_ADD2
00641         #define CMS_T8                                  // single call transmission
00642 #endif
00643 
00644 #ifdef CMS_TX_ADD3
00645         #define CMS_T9                                  // checking tx buffer
00646 #endif
00647 
00648 #ifdef CMS_TX_ADD4
00649         #define CMS_T11                                 // useful optional functions
00650         #define CMS_T12
00651 #endif
00652 
00653 #ifdef CMS_TX_ADD5
00654         #define CMS_CB5                                 // CMS tx filter
00655 #endif
00656 
00657 #ifdef CMS_TX_ADD7
00658       #ifdef OS8104A    
00659         #define CMS_T15                                 // set short retry time (OS8104A) 
00660         #define CMS_T16                                 // set number of long retries (OS8104A)
00661         #define CMS_T17                                 // get short retry time (OS8104A)
00662         #define CMS_T18                                 // get number of long retries (OS8104A)
00663       #endif
00664 #endif
00665 
00666 #endif  // CMS_TX_MIN
00667 
00668 
00669 
00670 // Control Message Service Rx Section
00671 //------------------------------------
00672 #ifdef CMS_RX_MIN                                       // minimum requirement
00673         #define CMS_0
00674         #define CMS_1
00675         #define CMS_R3
00676         #define CMS_R6
00677         #define CMS_R7
00678         #if (MAX_EXT_DATA > 0) || (defined CTRL_RX_FAKE)
00679             #define CMS_CB2
00680         #endif
00681         #define CMS_CB3
00682 
00683 #ifdef CMS_MSG_INTF         // Message based interface
00684         #define V_CMS_R5
00685 #else                       // Register based interface
00686         #define CMS_R5
00687 #endif
00688 
00689 #ifdef CMS_RX_ADD1                                      // message polling available
00690         #ifndef AMS_RX_MIN
00691             #define CMS_R1
00692             #define CMS_R2
00693         #endif
00694 #endif
00695 
00696 #ifdef CMS_RX_ADD2                                      // copy message to local memory
00697         #define CMS_R4
00698 #endif
00699 
00700 #ifdef CMS_RX_ADD3                                      // possibility to use addition receive input
00701         #define CMS_R30
00702         #define CMS_R32
00703 #endif
00704 
00705 #ifdef CMS_RX_ADD4                                      // additional rx filter
00706         #define CMS_CB4
00707 #endif
00708 
00709 #endif // CMS_RX_MIN
00710 
00711 
00712 
00713 // Appl. Message Service Tx Section
00714 //------------------------------------
00715 #ifdef AMS_TX_MIN                                       // minimum requirement
00716         #define AMS_0
00717         #define AMS_T1
00718         #define AMS_T3
00719         #define AMS_T4
00720         #define AMS_T5
00721         #define AMS_T6
00722         #define AMS_T7
00723         #define AMS_T8
00724         #define AMS_T9
00725         #define AMS_T10
00726         #define AMS_T11
00727         #define AMS_T12
00728         #define AMS_T14
00729         #define AMS_T51
00730         #define AMS_CB1
00731 
00732         #ifdef NS_AMS_AH                                // interface to AH of Layer II
00733             #define AMS_T13
00734         #endif
00735 
00736 #ifdef AMS_TX_ADD1                                      // checking tx buffer
00737         #define AMS_T2
00738 #endif
00739 
00740 
00741 #ifdef AMS_TX_ADD3                                      // encoding data field
00742         #define AMS_T20
00743         #define AMS_T21
00744         #define AMS_T22
00745         #define AMS_T23
00746 #endif
00747 
00748 #ifdef AMS_TX_ADD4                                      // sending large messages via handshake
00749         #define AMS_CB4
00750 #endif
00751 
00752 #ifdef AMS_TX_ADD5                                      // possibility to filter tx messages
00753         #define AMS_CB5
00754         #define AMS_T16
00755 #endif
00756 
00757 #ifdef AMS_TX_ADD6                                      // possibility to transmit and receive internal messages
00758         #define AMS_T16
00759         #define AMS_T30
00760         #define AMS_R30
00761         #define AMS_R32
00762         #define MCS_14                                      // shadowing of own address registers
00763 #endif
00764 
00765 #ifdef AMS_TX_ADD7                                      // possibility to postpone a failed transmission
00766         #define AMS_T40
00767 #endif
00768 
00769 #ifdef AMS_TX_ADD8                                      // possibility to use an external data field
00770     #define AMS_T50
00771 #endif
00772 
00773 #ifdef AMS_TX_ADD9
00774     #ifdef DEF_MID_LEVEL_RETRIES
00775         #if (DEF_MID_LEVEL_RETRIES > 255)
00776             #undef DEF_MID_LEVEL_RETRIES
00777             #define DEF_MID_LEVEL_RETRIES 255
00778         #endif
00779     #else
00780         #define DEF_MID_LEVEL_RETRIES 0
00781     #endif
00782 
00783     #ifdef DEF_MID_LEVEL_RETRIES_INT_PROC
00784         #if (DEF_MID_LEVEL_RETRIES_INT_PROC > 255)
00785             #undef DEF_MID_LEVEL_RETRIES_INT_PROC 
00786             #define DEF_MID_LEVEL_RETRIES_INT_PROC 255
00787         #endif
00788     #else
00789         #define DEF_MID_LEVEL_RETRIES_INT_PROC 0
00790     #endif
00791 #endif
00792 
00793 #ifdef AMS_TX_BYPASS_FILTER                             // Bypass filter AMS TX -> CMS TX
00794         #define AMS_T15
00795         #define AMS_CB6
00796 #endif
00797 
00798 #endif  // AMS_TX_MIN
00799 
00800 
00801 
00802 // Appl. Message Service Rx Section
00803 //------------------------------------
00804 #ifdef AMS_RX_MIN                                       // minimum requirement
00805         #define AMS_0
00806         #define AMS_R1
00807         #define AMS_R2
00808         #define AMS_R5
00809         #define AMS_R7
00810         #define AMS_R8
00811         #define AMS_R9
00812       #ifndef AMS_RX_NOSEG
00813         #define AMS_R10
00814       #endif
00815         #define AMS_R11
00816         #define AMS_R12
00817         #define AMS_CB2
00818         #define AMS_CB3
00819 
00820 #ifdef AMS_RX_ADD1                                      // message polling available
00821         #define AMS_R3
00822         #define AMS_R4
00823 #endif
00824 
00825 #ifdef AMS_RX_ADD2                                      // copy message to local memory
00826         #define AMS_R6
00827 #endif
00828 
00829 
00830 #ifdef AMS_RX_ADD3                                      // decoding data field
00831         #define AMS_R20
00832         #define AMS_R21
00833         #define AMS_R22
00834 #endif
00835 
00836 
00837 #ifdef AMS_RX_ADD4                                      // possibility to receive internal messages
00838         #define AMS_R30
00839         #define AMS_R32
00840 #endif
00841 
00842 #ifdef AMS_RX_ADD5                                      // Receive Buffer Extension
00843         #define AMS_R40
00844         #define AMS_R41
00845         #define AMS_R42
00846         #define AMS_CB7
00847         #define AMS_CB8
00848 #endif
00849 
00850 #ifdef AMS_RX_ADD6                                      // request rx buffer status
00851         #define AMS_R13
00852 #endif
00853 
00854 #ifdef AMS_RX_ADD5_OPT1                                 // 
00855         #define AMS_R43
00856 #endif
00857 
00858 #endif  // AMS_RX_MIN
00859 
00860 
00861 
00862 // Remote Control Service
00863 //------------------------------------
00864 #ifdef RCS_WRITE                                        // minimum requirement
00865         #define RCS_0                                   // for remote write
00866         #define RCS_1
00867         #define RCS_CB1
00868         #define CMS_T8
00869 #endif
00870 
00871 #ifdef RCS_READ                                         // minimum requirement
00872         #define RCS_0                                   // for remote read
00873         #define RCS_2
00874         #define RCS_5
00875         #define RCS_6
00876         #define RCS_CB2
00877         #define CMS_T8
00878 #endif
00879 
00880 
00881 // Synchron Channel Allocation Service
00882 //------------------------------------
00883 #ifdef SCS_SOURCE_ALLOC_MIN                             // allocate / deallocate minimum requirement
00884         #define SCS_0
00885         #define SCS_A1
00886         #define SCS_A2
00887         #define SCS_A6
00888         #define SCS_D1
00889         #define SCS_D2
00890         #define SCS_D6
00891         #define SCS_CB1
00892         #define SCS_CB2
00893         #define CMS_T8
00894 #endif
00895 
00896 #ifdef  SCS_SOURCE_RE_MIN                               // connect / disconnect minimum requirement
00897         #define SCS_R1
00898         #define SCS_R2
00899         #define SCS_R3
00900         #define SCS_R8
00901 #endif
00902 
00903 #ifdef SCS_SOURCE_ADD1                                  // single call functions for allocation and routing
00904         #define SCS_A5
00905         #define SCS_D3
00906 #endif
00907 
00908 #ifdef SCS_SOURCE_ADD2                                  // Source Port features of OS8104A
00909     #ifdef OS8104A
00910         #define SCS_A7
00911         #define SCS_A8
00912         #define SCS_R9
00913         #define SCS_R10
00914     #endif
00915 #endif
00916 
00917 #ifdef SCS_SINK_RE_MIN                                  // connect / disconnect minimum requirement
00918         #define SCS_R4
00919         #define SCS_R5
00920         #define SCS_R6
00921 #endif
00922 
00923 #ifdef SCS_ADD1                                         // useful optional functions on source and destination side
00924         #ifndef NO_DIRECT_REG_ACCESS
00925         #define SCS_R7  // SyncFindChannel() is not available if NO_DIRECT_REG_ACCESS is used
00926         #endif
00927 #endif
00928 
00929 #ifdef SCS_ADD2
00930         #define SCS_G1
00931         #define SCS_G2
00932         #define SCS_G3
00933         #define SCS_CB3
00934 #endif
00935 
00936 #ifdef SCS_ADD3
00937         #define SCS_B1
00938         #define SCS_CB4
00939 #endif
00940 
00941 
00942 #if ( (defined SCS_SOURCE_ALLOC_MIN) || (defined SCS_SOURCE_RE_MIN) || (defined SCS_SOURCE_ADD1) || (defined SCS_SINK_RE_MIN) )
00943 #if ( (defined OS8401) && (!defined SCS_NO_ADDR_CALC) )
00944         #error SCS_NO_ADDR_CALC must be defined, when using the SCS on OS8401, OS8801, OS8804, or OS8805
00945 #endif
00946 #endif
00947 
00948 #ifdef RE_MSG_INTF
00949     #undef SCS_R1
00950     #undef SCS_R4
00951 #endif
00952 
00953 // Transparent Channel Allocation Service
00954 //----------------------------------------
00955 #if (defined TCS_SOURCE_ALLOC) || (defined TCS_SOURCE_RE) || (defined TCS_SOURCE_ALLOC_RE) || (defined TCS_SINK_RE)
00956 #ifndef SP_SER
00957         #error Transparent Channel Allocation Service (TCS) is only available on serial source ports.
00958 #endif
00959 #ifndef OS8104
00960         #error Transparent Allocation Service (TCS) is only available on OS8104 transceiver.
00961 #endif
00962 #endif
00963 
00964 #ifdef TCS_SOURCE_ALLOC                                 // allocate / deallocate transparent data channels
00965         #define TCS_0
00966         #define TCS_1
00967         #define TCS_A1
00968         #define TCS_D1
00969 #endif
00970 
00971 
00972 #ifdef TCS_SOURCE_RE                                    // connect / disconnect transparent data channels
00973         #define TCS_0
00974         #define TCS_1
00975         #define TCS_R2
00976         #define TCS_R3
00977 #endif
00978 
00979 #ifdef TCS_SOURCE_ALLOC_RE                              // single call functions for transparent data channels
00980         #define TCS_0                                   // (TCS_SOURCE_ALLOC and TCS_SOURCE_RE are NOT required !!!)
00981         #define TCS_1
00982         #define TCS_A5
00983         #define TCS_D3
00984 #endif
00985 
00986 #ifdef TCS_SINK_RE                                      // connect / disconnect transparent data channels
00987         #define TCS_0
00988         #define TCS_1
00989         #define TCS_R5
00990         #define TCS_R6
00991 #endif
00992 
00993 
00994 // MOST Supervisor
00995 //------------------------------------
00996 
00997 
00998 #if (defined MSV_ADD3) && (defined OS8104A) && (!defined OS8104A_DYN)  
00999     #undef MSV_ADD3
01000 #endif
01001 
01002 #ifdef MSV_MINIMUM                                      // if Minimum Supervisor is selected
01003         #define MSV_M1
01004         #define MSV_M3
01005         #define MSV_M7
01006         #define MSV_M8
01007         #define MSV_M9
01008         #define MSV_M14
01009         #define MSV_M17
01010         #define MSV_M26
01011         #define MSV_CB1
01012         #define MSV_CB2
01013         #define MSV_CB5
01014         #define MSV_CB6
01015 #endif
01016 
01017 #ifdef MSV_EXTENDED                                     // if Extended Supervisor is selected
01018         #define MSV_E1
01019         #define MSV_E2
01020         #define MSV_E3
01021         #define MSV_E5
01022         #define MSV_E7
01023         #define MSV_E8
01024         #define MSV_E9
01025         #define MSV_E10
01026         #define MSV_E11
01027         #define MSV_E13
01028         #define MSV_E14
01029         #define MSV_E15
01030         #define MSV_E16
01031         #define MSV_E17
01032         #define MSV_E26
01033         #define MSV_CB1
01034         #define MSV_CB2
01035         #define MSV_CB3
01036         #define MSV_CB4
01037         #define MSV_CB5
01038         #define MSV_CB6
01039         #define MSV_CB7
01040         #define MSV_CB8
01041         #define MSV_CB9
01042         #define MSV_CB10
01043         #define MSV_CB11
01044         #define MSV_CB12
01045         #define MSV_CB13
01046         #define MSV_CB14
01047         #define MSV_CB15
01048         #define MSV_CB16
01049         #define MSV_CB17
01050 
01051     #ifdef MSV_ADD2
01052         #define MSV_CB20
01053         #define MSV_CB21
01054     #endif
01055     #ifdef MSV_ADD3
01056         #define MSV_E20
01057     #endif
01058     #ifdef MSV_ADD4
01059         #define MSV_E21 // MostStartUpExt()
01060     #endif
01061     #ifdef MSV_ADD5
01062         #define MSV_CB22
01063     #endif
01064 
01065 
01066 
01067 
01068     #ifdef MSV_ADD9
01069         #define MSV_E27
01070         #define MSV_E28
01071         #define MSV_E29
01072         #define MSV_CB28
01073     #endif
01074 
01075     #ifdef MSV_ADD10
01076       #ifdef OS8805
01077         #define PLL_LIMITING                               // Rx/Crystal/Rx switch Timer (PLL limiting)
01078       #endif
01079     #endif
01080 
01081 
01082 
01083 
01084 
01085 
01086 #endif  // MSV_EXTENDED
01087 
01088 #ifdef MSV_VIRTUAL
01089         #define MSV_V1
01090         #define MSV_V2
01091         #define MSV_V3
01092         #define MSV_V5
01093         #define MSV_V14
01094         #define MSV_V17
01095         #define MSV_V21
01096         #define MSV_CB3
01097         #define MSV_CB4
01098         #define MSV_CB5
01099         #define MSV_CB6
01100         #define MSV_CB7
01101         #define MSV_CB8
01102         #define MSV_CB9
01103         #define MSV_CB10
01104         #define MSV_CB11
01105         #define MSV_CB12
01106         #define MSV_CB13
01107         #define MSV_CB14
01108         #define MSV_CB15
01109         #define MSV_CB16
01110         #define MSV_CB17
01111         #define MSV_CB22
01112 
01113     #ifdef MSV_ADD2
01114         #define MSV_CB20
01115     #endif
01116 
01117 
01118 
01119 
01120     #ifdef MSV_ADD9
01121         #define MSV_V27
01122         #define MSV_V28
01123         #define MSV_V29
01124         #define MSV_CB28
01125     #endif
01126 
01127 
01128 #endif  // MSV_VIRTUAL
01129 
01130 
01131 // MOST Supervisor Abstraction Layer
01132 //------------------------------------
01133 #if (!defined MSV_EXTENDED) && (!defined MSV_VIRTUAL)
01134     #undef MSVAL_MIN
01135 #endif
01136 
01137 #ifdef MSVAL_MIN
01138         #define MSVAL_0
01139         #define MSVAL_1
01140         #define MSVAL_CB1
01141         #define MSVAL_CB2
01142         #define MSVAL_CB3
01143         #define MSVAL_CB4
01144         #define MSVAL_CB5
01145 #endif
01146 
01147 // MOST Transceiver Control Service
01148 //------------------------------------
01149 #ifdef MCS_MIN                                          // minimum requirement of MOST Control Service
01150         #define MCS_0
01151         #define MCS_9
01152         #define MCS_15
01153 
01154 #ifdef MCS_ADD1                                         // interrupt handling
01155         #define MCS_1
01156         #define MCS_2
01157 #endif
01158 
01159 #ifdef MCS_ADD2                                         // address setting and reading of position registers
01160         #define MCS_3
01161         #define MCS_4
01162         #define MCS_8
01163         #define MCS_12
01164 #endif
01165 
01166 #ifdef MCS_ADD3                                         // rmck frequency setting
01167         #define MCS_5
01168 #endif
01169 
01170 #ifdef MCS_ADD4                                         // mute/demute source data outputs
01171         #define MCS_6
01172         #define MCS_7
01173 #endif
01174 
01175 #ifdef MCS_ADD5                                         // Reading delay registers
01176   #ifndef NO_DIRECT_REG_ACCESS                          // These functions are not available
01177         #define MCS_10                                  // if using only the message based interface !
01178         #define MCS_11
01179   #endif
01180 #endif
01181 
01182 #ifdef MCS_ADD6                                         // access to alternative packet address
01183         #define MCS_13
01184 #endif
01185 
01186 
01187 
01188 #ifdef MCS_MASTER_ADD1                                  // pll inselect
01189         #define MCS_M1
01190 #endif
01191 
01192 #ifdef MCS_MASTER_ADD2                                  // bandwidth setting
01193         #define MCS_M2
01194 #endif
01195 
01196 #if (defined MCS_ADD7) && (defined SECONDARY_NODE)      // service receive buffer of secondary node and prepare error message
01197         #define MCS_20
01198         #define MCS_21
01199         #define MCS_22
01200 #endif
01201 
01202 #ifdef MCS_ADD9
01203         #define MCS_50
01204         #define MCS_CB50
01205 #endif
01206 
01207 #if (defined MCS_MSG_INTF) && (defined MNS_MSG_INTF)    // direct register access using the messages based
01208         #define MCS_30                                  // interface, which is provided by MNS_MSG_INTF.
01209         #define MCS_31                                  // It is a must to defined MNS_MSG_INTF also !
01210         #define MCS_32
01211         #define MCS_33
01212         #define MCS_CB30
01213         #define MCS_CB31
01214         #define MCS_CB32
01215         #define MCS_CB33
01216 #else                                                   // MCS_ADD8 is ignored, if MCS_MSG_INTF is enabled (same API functions)
01217     #ifdef MCS_ADD8                                     // additional functions for register access
01218         #define MCS_40                                  // when using the register based hardware layer interface
01219         #define MCS_41
01220         #define MCS_42
01221         #define MCS_43
01222         #define MCS_CB40
01223         #define MCS_CB41
01224         #define MCS_CB42
01225         #define MCS_CB43
01226     #endif
01227 #endif
01228 
01229 #endif  // MCS_MIN
01230 
01231 
01232 
01233 // Async Data Transmission Service
01234 // Tx - Section
01235 //------------------------------------
01236 #ifdef ADS_TX_MIN                                       // minimum requirement of Tx section
01237         #define ADS_0
01238         #define ADS_1
01239         #define ADS_T1
01240         #define ADS_T2
01241         #define ADS_T5
01242         #define ADS_T6
01243         #define ADS_T7
01244         #define ADS_T10
01245         #define ADS_CB2
01246 
01247 #ifdef ADS_TX_ADD1                                      // single call transmission
01248         #define ADS_T8
01249 #endif
01250 
01251 #ifdef ADS_TX_ADD2                                      // check tx buffer
01252         #define ADS_T9
01253 #endif
01254 
01255 
01256 #ifdef ADS_TX_ADD3                                      // tx complete event
01257         #define ADS_CB3
01258 #endif
01259 
01260 #endif  // ADS_TX_MIN
01261 
01262 
01263 
01264 // Async Data Transmission Service
01265 // Rx - Section
01266 //------------------------------------
01267 #ifdef ADS_RX_MIN                                       // minimum requirement of Rx section
01268         #define ADS_0
01269         #define ADS_1
01270         #define ADS_R3
01271         #define ADS_R5
01272         #define ADS_R6
01273         #define ADS_R7
01274         #define ADS_CB1
01275         #define ADS_CB2
01276 
01277 #ifdef ADS_RX_ADD1                                      // packet polling available
01278         #define ADS_R1
01279         #define ADS_R2
01280 #endif
01281 
01282 #ifdef ADS_RX_ADD2                                      // copy packet to local memory
01283         #define ADS_R4
01284 #endif
01285 
01286 #ifdef ADS_RX_ADD3
01287         #define ADS_CB4                                 // external rx filter
01288 #endif
01289 
01290 #ifdef ADS_RX_ADD4
01291         #define ADS_CB5                                 // notify captured error events
01292 #endif
01293 
01294 #endif  // ADS_RX_MIN
01295 
01296 
01297 
01298 
01299 
01300 
01301 
01302 
01303 //-------------------------------------------------------------------
01304 //  Predefine MOST register values
01305 //  depending on your choice in adjust.h
01306 //-------------------------------------------------------------------
01307 
01308 //-------------------------
01309 //  Register: SDC1
01310 //-------------------------
01311 #ifdef OS8104
01312 // Prepare Bit EDG
01313 //-----------------
01314 #if (EDG_SCK == 1)
01315     #define SDC1_EDG    EDG                         // rising edge
01316 #else
01317     #define SDC1_EDG    0                           // falling edge
01318 #endif
01319 
01320 // Prepare Bit DEL
01321 //-----------------
01322 #if (DEL_FSY == 1)
01323     #define SDC1_DEL    DEL                         // delay enable
01324 #else
01325     #define SDC1_DEL    0                           // no delay
01326 #endif
01327 
01328 // Prepare Bit POL
01329 //-----------------
01330 #if (POL_FSY == 1)
01331     #define SDC1_POL    POL                         // FSY = high indicates left sample
01332 #else
01333     #define SDC1_POL    0                           // FSY = high indicates right sample
01334 #endif
01335 
01336 // Prepare Bit I/O
01337 //-----------------
01338 #if (IO_FSY == 1)
01339     #define SDC1_IO     IO                          // FSY / SCK are outputs
01340 #else
01341     #define SDC1_IO     0                           // FSY / SCK are inputs
01342 #endif
01343 
01344 // Prepare Bit NBR
01345 //-----------------
01346 #if (SP_SER_CLOCKRATE == 48)
01347     #define SDC1_NBR    NBR                         // 48 Fs SCK clock rate
01348 #else
01349     #define SDC1_NBR    0                           // unequal 48 Fs SCK clock rate
01350 #endif
01351 
01352 // Prepare Bit SPD
01353 //-----------------
01354 #if (SP_SER_MODE > 4)
01355     #define SDC1_SPD    SPD                         // S/PDIF port enable
01356 #else
01357     #define SDC1_SPD    0                           // S/PDIF port disable
01358 #endif
01359 
01360 // Prepare Bit MT
01361 //-----------------
01362 #if (SOURCE_MUTE == 1)
01363     #define SDC1_MT     0                           // source output ports muted
01364 #else
01365     #define SDC1_MT     MT                          // source output ports in normal operation
01366 #endif
01367 
01368 // Prepare Bit TCE
01369 //-----------------
01370 #ifndef TCH_DISABLE
01371     #define TCH_DISABLE 0
01372 #endif
01373 #if ( (SP_SER_MODE == 2) || (SP_SER_MODE == 6) ) && (TCH_DISABLE != 1)
01374     #define SDC1_TCE    0                           // transparent channel enable
01375 #else
01376     #define SDC1_TCE    TCE                         // transparent channel disable
01377 #endif
01378 
01379 
01380 // combine all features
01381 //----------------------
01382 #define REG_SDC1        ( SDC1_EDG | SDC1_DEL | SDC1_POL | SDC1_IO | SDC1_NBR | SDC1_SPD | SDC1_MT | SDC1_TCE )
01383 
01384 #endif // OS8104
01385 
01386 
01387 
01388 //-------------------------
01389 //  Register: SDC2
01390 //-------------------------
01391 // Prepare SCK rate
01392 //-----------------
01393 #if ( (SP_SER_CLOCKRATE==8) && ((SP_SER_MODE==1)||(SP_SER_MODE==2)||(SP_SER_MODE==5)||(SP_SER_MODE==6)||(SP_SER_MODE==8)) )
01394     #define SCK_RATE    0x00    // 8 Fs
01395 #endif
01396 
01397 
01398 #if ( (SP_SER_CLOCKRATE==16) && ((SP_SER_MODE==1)||(SP_SER_MODE==2)||(SP_SER_MODE==5)||(SP_SER_MODE==6)||(SP_SER_MODE==8)) )
01399     #define SCK_RATE    0x20    // 16 Fs
01400 #endif
01401 
01402 #if ( (SP_SER_CLOCKRATE==32) && ((SP_SER_MODE==1)||(SP_SER_MODE==2)||(SP_SER_MODE==5)||(SP_SER_MODE==6)||(SP_SER_MODE==8)) )
01403     #define SCK_RATE    0x40    // 32 Fs
01404 #endif
01405 
01406 #if ( (SP_SER_CLOCKRATE==48) && ((SP_SER_MODE==1)||(SP_SER_MODE==2)||(SP_SER_MODE==5)||(SP_SER_MODE==6)||(SP_SER_MODE==8)) )
01407     #define SCK_RATE    0x60    // 64 Fs
01408 #endif
01409 
01410 #if ( (SP_SER_CLOCKRATE==64) && ((SP_SER_MODE==1)||(SP_SER_MODE==2)||(SP_SER_MODE==5)||(SP_SER_MODE==6)||(SP_SER_MODE==8)) )
01411     #define SCK_RATE    0x60    // 64 Fs
01412 #endif
01413 
01414 #if ( (SP_SER_MODE==3)||(SP_SER_MODE==9) )
01415     #define SCK_RATE    0x80    // 128 Fs
01416 #endif
01417 
01418 #if (SP_SER_MODE==4)
01419     #define SCK_RATE    0xA0    // 256 Fs
01420 #endif
01421 
01422 #ifndef SCK_RATE
01423     #define SCK_RATE    0x60    // Default: 64 Fs
01424 #endif
01425 
01426 #ifdef SP_PAR
01427     #undef SCK_RATE
01428     #define SCK_RATE    0xA0    // If SourcePort is in parallel mode
01429 #endif
01430 
01431 
01432 // Prepare MFSY
01433 //-----------------
01434 #if (MFSY_ENABLE == 1)
01435     #define MFSY_BIT    0x10    // speed of FSY is increased (2Fs or 4Fs)
01436 #else
01437     #define MFSY_BIT    0x00    // speed of FSY is not increased (1Fs)
01438 #endif
01439 
01440 
01441 
01442 // Prepare TC clock rate
01443 //----------------------
01444 #if ( (SP_SER_CLOCKRATE / TRANSPARENT_SAMPLE_RATE) == 1 )
01445     #define TCC_RATE    0x00    // SCK divided by 1
01446 #endif
01447 
01448 #if ( (SP_SER_CLOCKRATE / TRANSPARENT_SAMPLE_RATE) == 2 )
01449     #define TCC_RATE    0x04    // SCK divided by 2
01450 #endif
01451 
01452 #if ( (SP_SER_CLOCKRATE / TRANSPARENT_SAMPLE_RATE) == 4 )
01453     #define TCC_RATE    0x08    // SCK divided by 4
01454 #endif
01455 
01456 #if ( (SP_SER_CLOCKRATE / TRANSPARENT_SAMPLE_RATE) == 8 )
01457     #define TCC_RATE    0x0C    // SCK divided by 8
01458 #endif
01459 
01460 #ifndef TCC_RATE
01461     #define TCC_RATE    0x00    // Default: SCK divided by 1
01462 #endif
01463 
01464 // Prepare S/PDIF rate
01465 //----------------------
01466 #if (SP_SER_MODE > 6) && (defined OS8104A) && (!defined OS8104A_DYN)
01467     #error Source Port Mode not supported by OS8104A 
01468 #endif
01469 
01470 #if ( (SP_SER_MODE==5)||(SP_SER_MODE==6) )
01471     #define SPDIF_RATE  0x00    // 64 Fs
01472 #endif
01473 
01474 #if ( (SP_SER_MODE==8)||(SP_SER_MODE==9) )
01475     #define SPDIF_RATE  0x01    // 128 Fs
01476 #endif
01477 
01478 #if (SP_SER_MODE==10)
01479     #define SPDIF_RATE  0x02    // 256 Fs
01480 #endif
01481 
01482 #if ( (SP_SER_MODE==11)||(SP_SER_MODE==12) )
01483     #define SPDIF_RATE  0x03    // 512 Fs
01484 #endif
01485 
01486 
01487 #ifndef SPDIF_RATE
01488     #define SPDIF_RATE  0x00    // Default: 64 Fs
01489 #endif
01490 
01491 
01492 // combine the three clock rates
01493 //-------------------------------
01494 #define REG_SDC2    (SCK_RATE | MFSY_BIT | TCC_RATE | SPDIF_RATE)
01495 
01496 #define SPDIF_RATE_MASK 0x03
01497 
01498 
01499 //-------------------------
01500 //  Register: SDC3
01501 //-------------------------
01502 // Prepare Bit SIO
01503 //-----------------
01504 #if (SP_SER_MODE==11)
01505     #define SDC3_SIO    SIO     // S/PDIF 8x input
01506 #else
01507     #define SDC3_SIO    0       // S/PDIF 8x output
01508 #endif
01509 
01510 // Prepare Bit SPS
01511 //-----------------
01512 #if (SPDIF_SYNC == 1)
01513     #define SDC3_SPS    SPS     // generate independent S/PDIF output timing
01514 #else
01515     #define SDC3_SPS    0       // synchronize S/PDIF output timing to input
01516 #endif
01517 
01518 // Prepare bit MTI
01519 //-----------------
01520 #if (defined OS8104A) && (defined SOURCEPORT_MUTE)
01521     #define SDC3_MTI    MTI     // all Source Data Input Ports are muted 
01522 #else
01523     #define SDC3_MTI    0       // Source Data Input Ports are not muted
01524 #endif
01525 
01526 // Prepare bit SPEN
01527 //-----------------
01528 #if (defined OS8104A) && (defined SOURCEPORT_DISABLE)
01529     #define SDC3_SPEN   SPEN    // Source Data Port are disabled
01530 #else
01531     #define SDC3_SPEN   0       // Source Data Port are enabled
01532 #endif
01533 
01534 
01535 // combine all features
01536 //----------------------
01537 #define REG_SDC3        ( SDC3_SIO | SDC3_SPS | SDC3_MTI | SDC3_SPEN)
01538 
01539 
01540 //-------------------------
01541 //  Register: XCR
01542 //-------------------------
01543 // Prepare Bit SBY
01544 //-----------------
01545 #if (SOURCE_BYPASS == 1)
01546     #define XCR_SBY     SBY     // Source data bypass enable
01547 #else
01548     #define XCR_SBY     0       // Source data bypass disable
01549 #endif
01550 
01551 // Prepare Bit REN
01552 //-----------------
01553 #if (RMCK_ENABLE == 1)
01554     #define XCR_REN     0       // RMCK output enable
01555 #else
01556     #define XCR_REN     REN     // RMCK output disable
01557 #endif
01558 
01559 // Prepare XCR Basic Value
01560 //------------------------
01561 #define REG_XCR_BASIC   ( LBO | XCR_SBY | XCR_REN ) // Bits MTR, OE, ABY will prepared by Supervisor State Machine
01562 
01563 
01564 
01565 //-------------------------
01566 //  Register: XSR
01567 //-------------------------
01568 
01569 // Prepare Bit MSL
01570 //-----------------
01571 #if (MASK_ERR_SPDIF == 1)
01572     #define XSR_MSL     MSL     // S/PDIF lock error ignored
01573 #else
01574     #define XSR_MSL     0       // S/PDIF lock error captured
01575 #endif
01576 
01577 // Prepare Bit MXL
01578 //-----------------
01579 #if (MASK_ERR_TRANS == 1)
01580     #define XSR_MXL     MXL     // Transceiver lock error ignored
01581 #else
01582     #define XSR_MXL     0       // Transceiver lock error captured
01583 #endif
01584 
01585 // Prepare Bit ME
01586 //-----------------
01587 #if (MASK_ERR_CODING == 1)
01588     #define XSR_ME      ME      // Coding error ignored
01589 #else
01590     #define XSR_ME      0       // Coding error captured
01591 #endif
01592 
01593 
01594 // Combine all features
01595 //----------------------
01596     #define REG_XSR         (XSR_MSL | XSR_MXL | XSR_ME)
01597 
01598 
01599 //-------------------------
01600 //  Register: XSR2
01601 //-------------------------
01602 
01603 #if  (defined OS8104A) && (!defined RX_FIFO_DISABLE)
01604     #define REG_XSR2    (DFE)
01605 #else
01606     #define REG_XSR2    0x00
01607 #endif
01608     
01609 
01610 //-------------------------
01611 //  Register: CM1
01612 //-------------------------
01613 // Prepare Bits MX1..0          // These bits are ignored by Supervisor, if device is initialized as Slave.
01614 //---------------------         // In a Slave device the pll input is conected with the RX network receive input pin.
01615 #if (PLL_INPUT == 1)
01616     #define CM1_MX      0x01    // S/PDIF
01617 #elif (PLL_INPUT == 3)
01618     #define CM1_MX      0x03    // Bit clock (SCK)
01619 #else
01620     #define CM1_MX      0x02    // default (Master): Chrystal
01621 #endif
01622 
01623 // Prepare Bits XTL1..0
01624 //---------------------
01625 #if (XTL_DIVIDER == 512)
01626     #if (defined OS8104A) && (!defined OS8104A_DYN)
01627     #error XTL_DIVIDER == 512 is not valid for OS8104A 
01628     #endif
01629     #define CM1_XTL     0x08    // 512 Fs
01630 #elif (XTL_DIVIDER == 384)
01631     #define CM1_XTL     0x04    // 384 Fs
01632 #else
01633     #define CM1_XTL     0x00    // default: 256 Fs
01634 #endif
01635 
01636 // Prepare Bits RD2..0
01637 //---------------------
01638 #if (RMCK_DIVIDER == 256)
01639     #define CM1_RD      0x10    // 256 Fs
01640 #elif (RMCK_DIVIDER == 128)
01641     #define CM1_RD      0x20    // 128 Fs
01642 #elif (RMCK_DIVIDER == 64)
01643     #define CM1_RD      0x30    // 64 Fs
01644 #elif (RMCK_DIVIDER == 1536)
01645     #define CM1_RD      0x40    // 1536 Fs
01646 #elif (RMCK_DIVIDER == 1024)
01647     #define CM1_RD      0x50    // 1024 Fs
01648 #elif (RMCK_DIVIDER == 768)
01649     #define CM1_RD      0x60    // 768 Fs
01650 #elif (RMCK_DIVIDER == 512)
01651     #define CM1_RD      0x70    // 512 Fs
01652 #else
01653     #define CM1_RD      0x00    // default: 384 Fs
01654 #endif
01655 
01656 
01657 // Combine all features
01658 //----------------------
01659 #define REG_CM1         (CM1_MX | CM1_XTL | CM1_RD)
01660 
01661 
01662 
01663 
01664 //-------------------------
01665 //  Register: NC
01666 //-------------------------
01667 #ifdef OS8104A
01668 // Prepare Bit EDG
01669 //-----------------
01670 #ifdef CMS_TX_ADD7
01671     #define NC_VRE      VRE                         // Variable Reries enabled
01672 #else
01673     #define NC_VRE      0                           // Variable Reries disabled
01674 #endif
01675 
01676 #ifdef CHANNEL_MUTE_DISABLE
01677     #define NC_CME      0                           // Channel Mute disabled
01678 #else
01679     #define NC_CME      CME                         // Channel Mute enabled
01680 #endif
01681 
01682 #ifdef ASYNCH_INIT_ENABLE
01683     #define NC_ARE      ARE
01684 #else
01685     #define NC_ARE      0
01686 #endif
01687 
01688 // combine all features
01689 //----------------------
01690 #define REG_NC        (NC_ARE | NC_VRE | NC_CME)
01691 
01692 
01693 #endif
01694 
01695 
01696 
01697 //-------------------------
01698 //  Register: SBC
01699 //-------------------------
01700 #if (SBC_DEFAULT > 0x05) && (SBC_DEFAULT < 0x10)
01701     #define REG_SBC     SBC_DEFAULT
01702 #else
01703     #define REG_SBC     0x06
01704 #endif
01705 #define INT_ENABLE_INIT (0xF0|(INT_ENABLE_AFTER_RESET&0xF))
01706 
01707 
01708 
01709 #ifdef OS8104A
01710 //-------------------------
01711 //  Register: CM3
01712 //-------------------------
01713 
01714     #ifdef FREQ_REGULATOR_DISABLE
01715         #define CM3_FREN    0       // Frequency regulator feature disabled
01716         #define CM3_ASR     0       // don't care
01717         #define CM3_ACD     0       // don't care
01718     #else
01719         #define CM3_FREN    FREN    // Frequency regulator feature enabled
01720         #define CM3_ASR     ASR     // automatic switch to reference clock
01721         #define CM3_ACD     ACD     // crystal is disabled automatically after relock
01722     #endif
01723 
01724     #define REG_CM3  (CM3_FREN | CM3_ASR | CM3_ACD)
01725 
01726 //-------------------------
01727 //  Register: FRLO, FRHI
01728 //-------------------------
01729     #if (!defined OS8104A_FRLO) || (OS8104A_FRLO > 0x80) 
01730         #define REG_FRLO 0x7A
01731     #else 
01732         #define REG_FRLO OS8104A_FRLO
01733     #endif
01734 
01735 
01736     #if (!defined OS8104A_FRHI) || (OS8104A_FRHI < 0x80) 
01737         #define REG_FRHI 0x86
01738     #else 
01739         #define REG_FRHI OS8104A_FRHI
01740     #endif
01741 
01742 #endif  //OS8104A
01743 
01744 
01745 //-------------------------------------------------------------------
01746 //  OS8401 and derivatives only:
01747 //  Predefine register values
01748 //  depending on your choice in adjust.h
01749 //-------------------------------------------------------------------
01750 
01751 //-------------------------
01752 //  Register: CMCS
01753 //-------------------------
01754 
01755 // Prepare Bits MX1..0          // These bits are ignored by Supervisor, if device is initialized as Slave.
01756 //---------------------         // In a Slave device the pll input is conected with the RX network receive input pin.
01757 #if   (PLL_INPUT == 1)
01758     #define CMCS_MX     0x0003  // S/PDIF
01759 #elif (PLL_INPUT == 3)
01760     #define CMCS_MX     0x0001  // Bit clock (SCK)
01761 #else
01762     #define CMCS_MX     0x0000  // default (Master): Chrystal
01763 #endif
01764 
01765 
01766 // Prepare Bits XTL1..0
01767 //---------------------
01768 #if   (XTL_DIVIDER == 512)
01769     #define CMCS_XTL    0x0000  // 512 Fs
01770 #elif (XTL_DIVIDER == 384)
01771     #define CMCS_XTL    0x0004  // 384 Fs
01772 #else
01773     #define CMCS_XTL    0x0008  // default: 256 Fs
01774 #endif
01775 
01776 // Prepare Bits RD2..0
01777 //---------------------
01778 #if   (RMCK_DIVIDER == 256)
01779     #define CMCS_RD     0x0010  // 256 Fs
01780 #elif (RMCK_DIVIDER == 128)
01781     #define CMCS_RD     0x0020  // 128 Fs
01782 #elif (RMCK_DIVIDER == 64)
01783     #define CMCS_RD     0x0030  // 64 Fs
01784 #elif (RMCK_DIVIDER == 1536)
01785     #define CMCS_RD     0x0040  // 1536 Fs
01786 #elif (RMCK_DIVIDER == 1024)
01787     #define CMCS_RD     0x0050  // 1024 Fs
01788 #elif (RMCK_DIVIDER == 768)
01789     #define CMCS_RD     0x0060  // 768 Fs
01790 #elif (RMCK_DIVIDER == 512)
01791     #define CMCS_RD     0x0070  // 512 Fs
01792 #else
01793     #define CMCS_RD     0x0000  // default: 384 Fs
01794 #endif
01795 
01796 // Prepare Bit /REN
01797 //---------------------
01798 #if (RMCK_ENABLE == 1)
01799     #define CMCS_RDIS   0x0000  // RMCK enable
01800 #else
01801     #define CMCS_RDIS   0x0080  // RMCK disable (high impedance)
01802 #endif
01803 
01804 
01805 // Combine features     (RMCK divider, Crystal divider, PLL mux select, RMCK disable)
01806 //----------------------
01807 #define REG_CMCS_SAH    (CMCS_RD | CMCS_XTL | CMCS_MX | CMCS_RDIS)
01808 
01809 
01810 
01811 //---------------------------
01812 //  Register: SDC1 (OS8401)
01813 //---------------------------
01814 #ifdef OS8401
01815 // Prepare Bit EDG
01816 //-----------------
01817 #if (EDG_SCK == 1)
01818     #define SDC1_EDG    EDG                         // rising edge
01819 #else
01820     #define SDC1_EDG    0                           // falling edge
01821 #endif
01822 
01823 // Prepare Bit DEL
01824 //-----------------
01825 #if (DEL_FSY == 1)
01826     #define SDC1_DEL    DEL                         // delay enable
01827 #else
01828     #define SDC1_DEL    0                           // no delay
01829 #endif
01830 
01831 // Prepare Bit POL
01832 //-----------------
01833 #if (POL_FSY == 1)
01834     #define SDC1_POL    POL                         // FSY = high indicates left sample
01835 #else
01836     #define SDC1_POL    0                           // FSY = high indicates right sample
01837 #endif
01838 
01839 // Prepare Bit NBR
01840 //-----------------
01841 #if (SP_SER_CLOCKRATE == 48)
01842     #define SDC1_NBR 0x08                           // 48 Fs SCK clock rate
01843 #elif (SP_SER_CLOCKRATE == 32)
01844     #define SDC1_NBR 0x10                           // 32 Fs SCK clock rate
01845 #else
01846     #define SDC1_NBR 0                              // 64 Fs SCK clock rate (default)
01847 #endif
01848 
01849 
01850 // Prepare Bits SPD and I/O in EGPIO mode (OS8805)
01851 //------------------------------------------------
01852 #if (SP_DISABLE == 1) && (defined OS8805)
01853     #define SDC1_SPD        0x04                    // Enable EGPIO mode in OS8805, source ports are disabled
01854     #define SDC1_IO         0x02                    // Setting IO_FSY in adjust.h is don't care.
01855 #else
01856 // Prepare Bit SPD
01857 //-----------------
01858     #if (SP_SER_MODE > 4)
01859         #define SDC1_SPD    0x04                    // S/PDIF port enable  (Bit2=1)
01860         #ifdef IO_FSY
01861          #undef  IO_FSY
01862          #define IO_FSY 0
01863         #endif
01864     #else
01865         #define SDC1_SPD    0                       // S/PDIF port disable (Bit2=0)
01866     #endif
01867 
01868 // Prepare Bit I/O
01869 //-----------------
01870     #if (IO_FSY == 1)
01871         #define SDC1_IO     0x02                    // FSY / SCK are outputs (Bit1=1)
01872     #else
01873         #define SDC1_IO     0                       // FSY / SCK are inputs  (Bit1=0)
01874     #endif
01875 #endif // #if (SP_DISABLE == 1) && (defined OS8805)
01876 
01877 
01878 // Prepare Bit MT
01879 //-----------------
01880 #if (SOURCE_MUTE == 1)
01881     #define SDC1_MT     0                           // source output ports muted
01882 #else
01883     #define SDC1_MT     0x01                        // source output ports in normal operation
01884 #endif
01885 
01886 
01887 
01888 // combine all features
01889 //----------------------
01890 #define REG_SDC1        ( SDC1_EDG | SDC1_DEL | SDC1_POL | SDC1_NBR | SDC1_SPD | SDC1_IO | SDC1_MT )
01891 
01892 #endif // OS8401
01893 
01894 
01895 
01896 
01897 //-------------------------------------------------------------------
01898 //  Define dummy macros, if not otherwise defined
01899 //-------------------------------------------------------------------
01900 #ifndef RES_MNSP_BEGIN
01901  #define RES_MNSP_BEGIN                     // Get Ressource:       MnsPending
01902 #endif
01903 
01904 #ifndef RES_MNSP_END
01905  #define RES_MNSP_END                       // Release Ressource:   MnsPending
01906 #endif
01907 
01908 #ifndef RES_MNSPA_BEGIN
01909  #define RES_MNSPA_BEGIN                    // Get Ressource:       MnsPendingAsync  (only needed if ADS implemented)
01910 #endif
01911 
01912 #ifndef RES_MNSPA_END
01913  #define RES_MNSPA_END                      // Release Ressource:   MnsPendingAsync  (only needed if ADS implemented)
01914 #endif
01915 
01916 
01917 
01918 //-------------------------------------------------------------------
01919 //  Default Macros to reset the interrupt request:
01920 //
01921 //  Please note:
01922 //  These default macros can be replaced by the user defined
01923 //  macros, which are defined in adjust.h.
01924 //  The macro has to clear the Interrupt flag in MOST Chip
01925 //  and can be used to clear the request flag of the Operating
01926 //  System if required.
01927 //-------------------------------------------------------------------
01928 
01929 #ifndef MOST_INT_RESET      // clear interrupt flags in the Message Control Register:
01930  #define MOST_INT_RESET(a)      MOST_WRITE(MSGC,(a))
01931 #endif
01932 //-------------------------------------------------------------------
01933 
01934 #ifndef MOST_AINT_RESET     // clear interrupt flags in the Packet Control Register:
01935  #ifdef PADT
01936   #define MOST_AINT_RESET(a)    PAR_A_WRITE_SINGLE_BYTE(0,(byte)PCTC,(a))   // Using the Parallel Asynchronous Source Port Interface *)
01937  #else
01938   #define MOST_AINT_RESET(a)    MOST_WRITE(PCTC,(a))                        // Using the Controll Port Interface *)
01939  #endif
01940 #endif
01941                             //
01942                             //      *) Please note:
01943                             //
01944                             //      If you want to define your own MOST_AINT_RESET macro in adjust.h,
01945                             //      you have to observe that the macro PADT cannot be accessed in adjust.h,
01946                             //      since it is defined at a later moment. But you simply have to know, what
01947                             //      interface must be used: the control port interface or the source port interface.
01948 
01949 //-------------------------------------------------------------------
01950 
01951 #ifndef MOST_INT_RESET_SEC  // clear interrupt flags in the Message Control Register of secondary node:
01952  #define MOST_INT_RESET_SEC(a)      MOST_WRITE_SEC(MSGC,(a))
01953 #endif
01954 
01955 //-------------------------------------------------------------------
01956 
01957 
01958 
01959 #endif  // _MOSTDEF1_H
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