/home/hillier_g/checkout/most4linux/libnetservices/include/smsc/mostreg.h

00001 /*
00002 ==============================================================================
00003 
00004 Project:        MOST NetServices 
00005 Module:         Register Definitions of MOST Transceiver OS8104
00006 File:           MostReg.h
00007 Version:        1.10.03 
00008 Language:       C
00009 Author(s):      S.Kerber
00010 Date:           25.Feb.2005
00011 
00012 FileGroup:      Layer I
00013 Customer ID:    20D0FF0B011003.N.SIERE
00014 FeatureCode:    FCR1
00015 ------------------------------------------------------------------------------
00016 
00017                 (c) Copyright 1998-2005
00018                 Oasis SiliconSystems AG
00019                 All Rights Reserved
00020 
00021 ------------------------------------------------------------------------------
00022 
00023 
00024 
00025 Modifications
00026 ~~~~~~~~~~~~~
00027 Date    By      Description
00028 
00029 ==============================================================================
00030 */
00031 
00032 #ifndef _MOSTREG_H
00033 #define _MOSTREG_H
00034 
00035 
00036 #ifndef _ADJUST_H
00037     // Due to downward capatibility (no macro _ADJUST_H in older ADJUST.H file):
00038     // When MOSTREG.H is used without ADJUST.H, the macro MOST_MAP_16BIT must be
00039     // defined, before MOSTREG.H is included, but only in case of 16Bit MAP mode
00040     // is demanded. When 8Bit MAP mode is desired, no macro has to be defined.
00041     // When you use MOSTREG.H in the ordinary way (with ADJUST.H) you can
00042     // ignore this hint.
00043 #endif
00044 
00045 #ifndef _MOSTDEF1_H
00046 #ifndef USE_OWN_TYPE_DEFINITION 
00047 typedef unsigned char byte;
00048 typedef unsigned short int word;
00049 #endif
00050 #endif
00051 
00052 
00053 #ifdef MOST_MAP_16BIT
00054     #define tMostMap        word    
00055     #define MOST_MAP_MASK   0xFFFF
00056 #else
00057     #define tMostMap        byte
00058     #define MOST_MAP_MASK   0xFF
00059 #endif      
00060 
00061 
00062 
00063 
00064 
00065 //-------------------------------------------------------------------
00066 // Registers of Page0
00067 //-------------------------------------------------------------------
00068 #define     RIT             (tMostMap)0x0000                        // Routing information table
00069 #define     RIT_LENGTH      (tMostMap)0x0080                        // Length of Routing Section
00070 #define     XCR             (tMostMap)0x0080                        // Transceiver-Control
00071 #define     XSR             (tMostMap)0x0081                        // Transceiver-Status
00072 #define     SDC1            (tMostMap)0x0082                        // Source Data Control 1
00073 #define     CM1             (tMostMap)0x0083                        // Clock-Manager 1
00074 #define     NC              (tMostMap)0x0084                        // Network Control
00075 #define     MSGC            (tMostMap)0x0085                        // Message Control
00076 #define     MSGS            (tMostMap)0x0086                        // Message Status
00077 #define     NPR             (tMostMap)0x0087                        // Node position
00078 #define     IE              (tMostMap)0x0088                        // Interrupt enable register
00079 #define     GA              (tMostMap)0x0089                        // Group Address
00080 #define     NAH             (tMostMap)0x008A                        // Node Address High
00081 #define     NAL             (tMostMap)0x008B                        // Node Address Low
00082 #define     SDC2            (tMostMap)0x008C                        // Source Data Control 2
00083 #define     SDC3            (tMostMap)0x008D                        // Source Data Control 3
00084 #define     CM2             (tMostMap)0x008E                        // Clock-Manager 2
00085 #define     NDR             (tMostMap)0x008F                        // Node Delay
00086 #define     MPR             (tMostMap)0x0090                        // Maximum Position
00087 #define     MDR             (tMostMap)0x0091                        // Maximum Delay
00088 #define     CM3             (tMostMap)0x0092                        // Clock-Manager 3 
00089 #define     CM4             (tMostMap)0x0093                        // Clock-Manager 4 
00090 #define     FRHI            (tMostMap)0x0094                        // Frequency Regulator High Control
00091 #define     FRLO            (tMostMap)0x0095                        // Frequency Regulator Low Control
00092 #define     SBC             (tMostMap)0x0096                        // Synchronous Bandwidth Control
00093 #define     XSR2            (tMostMap)0x0097                        // Transceiver-Status 2
00094 #define     RCMB            (tMostMap)0x00A0                        // Receive Ctrl Message Buffer
00095 #define     RTYP            (tMostMap)0x00A0                        // Receive Message Type
00096 #define     RSAH            (tMostMap)0x00A1                        // Source Address High
00097 #define     RSAL            (tMostMap)0x00A2                        // Source Address Low
00098 #define     RCD0            (tMostMap)0x00A3                        // Receive Control Data 0
00099 #define     RCD1            (tMostMap)0x00A4                        // Receive Control Data 1           
00100 #define     RCD2            (tMostMap)0x00A5                        // Receive Control Data 2
00101 #define     RCD3            (tMostMap)0x00A6                        // Receive Control Data 3
00102 #define     RCD4            (tMostMap)0x00A7                        // Receive Control Data 4
00103 #define     RCD5            (tMostMap)0x00A8                        // Receive Control Data 5
00104 #define     RCD6            (tMostMap)0x00A9                        // Receive Control Data 6
00105 #define     RCD7            (tMostMap)0x00AA                        // Receive Control Data 7
00106 #define     XTIM            (tMostMap)0x00BE                        // Xmit Retry Time
00107 #define     XRTY            (tMostMap)0x00BF                        // Xmit Retry
00108 #define     XCMB            (tMostMap)0x00C0                        // Xmit Control Message Buffer
00109 #define     XPRI            (tMostMap)0x00C0                        // Xmit Priority
00110 #define     XTYP            (tMostMap)0x00C1                        // Xmit Message Type
00111 #define     XTAH            (tMostMap)0x00C2                        // Target Address High
00112 #define     XTAL            (tMostMap)0x00C3                        // Target Address Low
00113 #define     XCD0            (tMostMap)0x00C4                        // Xmit Control Data 0         
00114 #define     XCD1            (tMostMap)0x00C5                        // Xmit Control Data 1
00115 #define     XCD2            (tMostMap)0x00C6                        // Xmit Control Data 2
00116 #define     XCD3            (tMostMap)0x00C7                        // Xmit Control Data 3
00117 #define     XCD4            (tMostMap)0x00C8                        // Xmit Control Data 4
00118 #define     XCD5            (tMostMap)0x00C9                        // Xmit Control Data 5
00119 #define     XCD6            (tMostMap)0x00CA                        // Xmit Control Data 6
00120 #define     XCD7            (tMostMap)0x00CB                        // Xmit Control Data 7
00121 #define     XTS             (tMostMap)0x00D5                        // Xmit Transfer Status
00122 #define     PCTC            (tMostMap)0x00E2                        // Packet Control
00123 #define     PCTS            (tMostMap)0x00E3                        // Packet Status
00124 #define     PCMA            (tMostMap)0x00E6                        // Parallel Combined Mode Register
00125 #define     APAH            (tMostMap)0x00E8                        // Alternat. Packet Addr. High
00126 #define     APAL            (tMostMap)0x00E9                        // Alternat. Packet Addr. Low
00127 #define     PSTX            (tMostMap)0x00EA                        // Packet Start Tx Register
00128 #define     PLDT            (tMostMap)0x00EC                        // Packet Length for Data Xmit
00129 #define     PPI             (tMostMap)0x00F2                        // Packet Priority
00130 #define     PAGE            (tMostMap)0x00FF                        // Swap RAM page 
00131                                                                         // (available in all pages)
00132 //-------------------------------------------------------------------
00133 
00134 
00135 
00136 //-------------------------------------------------------------------
00137 // Registers of Page1
00138 //-------------------------------------------------------------------
00139 #define     ARP             (tMostMap)(0x0180 & MOST_MAP_MASK)      // Async Rcv. Packet Buffer
00140 #define     ARTH            (tMostMap)(0x0180 & MOST_MAP_MASK)      // Received Tgt.Addr. High
00141 #define     ARTL            (tMostMap)(0x0181 & MOST_MAP_MASK)      // Received Tgt.Addr. Low
00142 #define     ASAH            (tMostMap)(0x0182 & MOST_MAP_MASK)      // Source Address High
00143 #define     ASAL            (tMostMap)(0x0183 & MOST_MAP_MASK)      // Source Address Low
00144 #define     ARD0            (tMostMap)(0x0184 & MOST_MAP_MASK)      // Async Receive Data 0
00145 #define     AXP             (tMostMap)(0x01C0 & MOST_MAP_MASK)      // Async. Xmit Packet Buffer
00146 #define     ATAH            (tMostMap)(0x01C0 & MOST_MAP_MASK)      // Received Tgt.Addr. High
00147 #define     ATAL            (tMostMap)(0x01C1 & MOST_MAP_MASK)      // Received Tgt.Addr. Low
00148 #define     AXD0            (tMostMap)(0x01C2 & MOST_MAP_MASK)      // Async Receive Data 0
00149 //-------------------------------------------------------------------
00150 
00151 
00152 
00153 //-------------------------------------------------------------------
00154 // Registers of Page3
00155 //-------------------------------------------------------------------
00156 #define     CRA             (tMostMap)(0x0380 & MOST_MAP_MASK)      // Allocation Table
00157 #define     XLRTY           (tMostMap)(0x03C0 & MOST_MAP_MASK)      // Transmit Long Retry Register
00158 #define     XSTIM           (tMostMap)(0x03C1 & MOST_MAP_MASK)      // Transmit Short Retry Time Register
00159 //-------------------------------------------------------------------
00160 
00161 
00162 
00163 //-------------------------------------------------------------------
00164 // Registers available in Standalone Mode only
00165 //-------------------------------------------------------------------
00166 #define     SIMB            (tMostMap)0x00EB                        // Standalone I2C Msg Buffer
00167 #define     SIMC            (tMostMap)0x00EB                        // Count of bytes to send
00168 #define     SITA            (tMostMap)0x00EC                        // I2C target address
00169 #define     SIMA            (tMostMap)0x00ED                        // I2C MAP
00170 #define     SITD0           (tMostMap)0x00EE                        // I2C transfer Data 0
00171 #define     SITD1           (tMostMap)0x00EF                        // I2C transfer Data 1
00172 #define     SITD2           (tMostMap)0x00F0                        // I2C transfer Data 2
00173 #define     SITD3           (tMostMap)0x00F1                        // I2C transfer Data 3
00174 #define     SITC            (tMostMap)0x00F2                        // I2C transfer control
00175 //-------------------------------------------------------------------
00176 
00177 
00178 
00179 
00180 
00181 
00182 
00183 
00184 
00185 
00186 
00187 //-------------------------------------------------------------------
00188 // Bits of XCR
00189 //-------------------------------------------------------------------
00190 #define     MTR             (byte)0x80      // Master/Slave
00191 #define     OE              (byte)0x40      // Output enable
00192 #define     LBO             (byte)0x20      // Legacy Bypass Operation (since OS8104A)  
00193 #define     LPW             (byte)0x10      // Low power wake-up
00194 #define     SAN             (byte)0x08      // Stand-Alone mode
00195 #define     SBY             (byte)0x04      // Source data bypass
00196 #define     ABY             (byte)0x02      // All bypass
00197 #define     REN             (byte)0x01      // RMCK enable
00198 #define     O_EN            (byte)0x40      // Mask: Output enable  
00199 #define     O_DIS           (byte)0xBF      // Mask: Output disable     
00200 
00201 //-------------------------------------------------------------------
00202 // Bits of XSR
00203 //-------------------------------------------------------------------
00204 #define     FRA             (byte)0x80      // Frequency Regulator Active (OS8104A only)
00205 #define     MSL             (byte)0x40      // Mask S/PDIF lock error
00206 #define     MXL             (byte)0x20      // Mask transceiver lock error
00207 #define     ME              (byte)0x10      // Mask coding error
00208 #define     ERR             (byte)0x08      // All Error capture
00209 #define     FRLR            (byte)0x04      // Frequency Regulator locked to reference clock (OS8104A only)
00210 #define     ESL             (byte)0x02      // Error capture S/PDIF
00211 #define     EXL             (byte)0x01      // Error capture transceiver
00212 
00213 //-------------------------------------------------------------------
00214 // Bits of SDC1
00215 //-------------------------------------------------------------------
00216 #define     EDG             (byte)0x80      // active edge of SCK
00217 #define     DEL             (byte)0x40      // Delay first bit against FSY
00218 #define     POL             (byte)0x20      // Polarity of FSY
00219 #define     IO              (byte)0x10      // I/O Select of FSY and SCK
00220 #define     NBR             (byte)0x08      // Number of SCK cycles per frame
00221 #define     SPD             (byte)0x04      // S/PDIF port enable
00222 #define     MT              (byte)0x02      // Mute source data outputs
00223 #define     TCE             (byte)0x01      // Transparent channel enable
00224 
00225 //-------------------------------------------------------------------
00226 // Bits of CM1
00227 //-------------------------------------------------------------------
00228 #define     PLD             (byte)0x80      // PLL disable
00229 
00230 //-------------------------------------------------------------------
00231 // Bits of NC
00232 //-------------------------------------------------------------------
00233 #define     ARE             (byte)0x08      // Asynchronous Initialization Enable (OS8104A only)
00234 #define     VRE             (byte)0x04      // Variable Retry Enable
00235 #define     CME             (byte)0x02      // Channel Mute Enable
00236 
00237 //-------------------------------------------------------------------
00238 // Bits of CM3
00239 //-------------------------------------------------------------------
00240 // OS8104A only 
00241 #define     ENH             (byte)0x40      // Enhanced Mode Active
00242 #define     FREN            (byte)0x10      // Frequency Regulator Enable
00243 #define     ASR             (byte)0x08      // Automatic Switch to Crystal Enable
00244 #define     ACD             (byte)0x04      // Automatic Crystal Disable
00245 #define     FRR             (byte)0x02      // Frequency Regulator Reset
00246 
00247 //-------------------------------------------------------------------
00248 // Bits of MSGC
00249 //-------------------------------------------------------------------
00250 #define     STX             (byte)0x80      // Start transmission
00251 #define     RBE             (byte)0x40      // Receive buffer enable
00252 #define     SAI             (byte)0x10      // Start address initialisation
00253 #define     RALC            (byte)0x08      // Reset Allocation change interrupt
00254 #define     RERRPO          (byte)0x04      // Reset Error or Power-on after start-up interrupt
00255 #define     RMTX            (byte)0x02      // Reset Message transmitted interrupt
00256 #define     RMRX            (byte)0x01      // Reset Message received interrupt
00257 
00258 //-------------------------------------------------------------------
00259 // Bits of MSGS
00260 //-------------------------------------------------------------------
00261 #define     RBS             (byte)0x80      // Receive buffer status
00262 #define     TXR             (byte)0x40      // Transmission result
00263 #define     ALC             (byte)0x08      // Allocation change
00264 #define     ERRPO           (byte)0x04      // Error or Power-on after start-up
00265 #define     MTX             (byte)0x02      // Message transmitted
00266 #define     MRX             (byte)0x01      // Message received
00267 
00268 //-------------------------------------------------------------------
00269 // Bits of IER
00270 //-------------------------------------------------------------------
00271 #define     IALC            (byte)0x08      // Interrupt on Allocation change
00272 #define     IERR            (byte)0x04      // Interrupt on Error or Power-on after start-up
00273 #define     IMTX            (byte)0x02      // Interrupt on Message transmitted
00274 #define     IMRX            (byte)0x01      // Interrupt on Message received
00275 
00276 //-------------------------------------------------------------------
00277 // Bits of SDC3
00278 //-------------------------------------------------------------------
00279 #define     SIO             (byte)0x80      // S/PDIF in 8x mode IO select
00280 #define     SPS             (byte)0x08      // S/PDIF sync source
00281 #define     MTI             (byte)0x02      // Mute Source Port inputs
00282 #define     SPEN            (byte)0x01      // Source Port Enable  
00283 
00284 //-------------------------------------------------------------------
00285 // Bits of CM2
00286 //-------------------------------------------------------------------
00287 #define     LOK             (byte)0x80      // PLL lock status
00288 #define     NAC             (byte)0x40      // Network activity status
00289 #define     ZP              (byte)0x20      // Zero power mode enable
00290 #define     LP_MODE         (byte)0x10      // Low power mode enable
00291 #define     FCA             (byte)0x02      // Force Crystal Active  (OS8104A only) 
00292 
00293 //-------------------------------------------------------------------
00294 // Bits of XSR2
00295 //-------------------------------------------------------------------
00296 #define     DFE             (byte)0x08      // Deep FIFO Enable
00297 #define     INV             (byte)0x02      // RX Inversion Control
00298 
00299 //-------------------------------------------------------------------
00300 // Bits of PCTC
00301 //-------------------------------------------------------------------
00302 #define     RAF             (byte)0x10      // Reset bit AF in PCTS
00303 #define     RAC             (byte)0x08      // Reset bit AC in PCTS
00304 #define     RATX            (byte)0x02      // Clear packet transmitted interrupt
00305 #define     RARX            (byte)0x01      // Unlock the Asynchr. Receive Packet Buffer mARP
00306 
00307 //-------------------------------------------------------------------
00308 // Bits of PCTS
00309 //-------------------------------------------------------------------
00310 #define     AF              (byte)0x10      // Packet reject status (mARP full)
00311 #define     AC              (byte)0x08      // Packet reject status (CRC failed)
00312 #define     ARF             (byte)0x04      // Receiption failed (mARP full or CRC failed)
00313 #define     ATX             (byte)0x02      // Packet transmitted event
00314 #define     ARX             (byte)0x01      // Packet received event
00315 
00316 //-------------------------------------------------------------------
00317 // Bits of PCMA
00318 //-------------------------------------------------------------------
00319 #define     APCM            (byte)0x01      // Parallel Combined Mode Active
00320 
00321 //-------------------------------------------------------------------
00322 // Bits of PSTX
00323 //-------------------------------------------------------------------
00324 #define     ASTX            (byte)0x80      // Start packet transmission
00325 
00326 
00327 
00328 #endif // _MOSTREG_H
00329 
00330 
00331 
00332 
00333
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